High-speed serial links may be used, for example, to carry data between two CPUs or other processing devices. High speed serial links, such as those used in Peripheral Component Interconnect (PCI) Express, usually support some form or forms of low power modes which the link can go into when there is no system data to transmit and the link is inactive. For instance, some high-speed serial links may use power at transmit circuitry (e.g., data drivers) and/or at receive circuitry (e.g., data capture circuitry) as data is transmitted over the links. Low-power modes seek to save some of that power by, e.g., turning off transmit circuitry and/or receive circuitry.
The level of power savings has a general relationship to the time it takes to enter into and exit out of that power savings state; that is, the usual expectation is that the greater the power savings of a state, the longer it takes to enter or exit that state. Long entry and exit times are usually undesirable due to the impact on computer system performance. When a link is in a low power mode and system data traffic becomes available again, the system may then have to wait for the link to exit the low power mode before it can be transferred.
Long low power mode entry times may reduce the time in the low power mode, which may reduce the amount of power saved. Furthermore, if the link is designed such that it fully enters the low power mode before it can exit, system performance may be doubly affected if data traffic shows up right after the link starts its sequence to enter the low power savings state and data traffic then waits for both the entry and exit times.
Typical high speed serial links have low power mode entry and exit times measured in milliseconds or microseconds. Specifically, some serial links may include a plurality of channels, and a conventional low power mode technique may include shutting down the receive side circuitry for some or all of the serial links. However, during that time the serial links have been shut down, the receiver may lose a phase lock on its input data signal and may also lose its equalization and gain settings. The exit time (i.e., returning to active mode from a low-power mode) may include time to lock on a phase of the input data signal and establish equalization and gain settings.
Accordingly, there is a need in the art for systems and methods that provide real power savings through use of low-power modes and also reduce entry and exit times compared to conventional solutions.